This tool takes a SystemVerilog file as input and produces as output the module(s) declared in that file, along with the module(s) instantiated in each one of those module declarations. It uses sv-parser and is adapted from svlint.
The Verilog language has contains features for defining configs and libraries. However, these features are not well-supported by open-source tools, and even some commercial synthesis tools. By extracting a list of modules defined and instantiated in a file, a user can work around this problem by constructing their own design hierarchy outside of Verilog, and then passing that list of files back into the simulator / synthesis tool.
You can download a binary for your system from the Releases tab. This method does not require Rust be installed.
Alternatively, you can install the package with Cargo: ```shell
cargo install svinst ```
The svinst binary accepts one or more SystemVerilog files as input, and prints a YAML-formatted representation of the modules defined and instantiated in those files:
```shell
svinst verilog/test.sv files: - filename: "verilog/test.sv" moddefs: - modname: "A" modinsts: - modname: "B" modinsts: - modname: "C" modinsts: - modname: "A" instname: "I0" - modname: "B" instname: "I1" - modname: "D" modinsts: - modname: "X" instname: "I0" - modname: "Y" instname: "I1" ```
If there are any parsing errors, the return code of svinst is nonzero, and the error message(s) will be sent to stderr:
```shell
svinst verilog/broken.sv > /dev/null parse failed: "verilog/broken.sv" verilog/broken.sv:5:10 | 5 | endmodule | echo $? 1 ```
It is also possible to specify files to be included on the command line, via the -i INCLUDE_PATH option. Multiple include paths may be specified; pass each separately via individual -i options.
```shell
svinst verilog/inctest.sv -i verilog/ files: - filename: "verilog/inctest.sv" moddefs: - modname: "inctop" modinsts: - modname: "modnamefromincsv" inst_name: "I0" ```
Pre-processor defines can be set from the command line as well. In this example, the first define has both a name and a value, controlling the name of the instantiated module from a define variable. The second define has only a name, and it causes a second module to be instantiated only if it has be defined.
```shell
svinst verilog/deftest.sv -d MODULENAME=modulenamefromdefine -d EXTRAINSTANCE files: - filename: "verilog/deftest.sv" moddefs: - modname: "deftop" modinsts: - modname: "modulenamefromdefine" instname: "I0" - modname: "modulefromifdef" inst_name: "I1" ```
It is also possible to generate the full syntax tree for SystemVerilog file(s) using the full-tree option. The output is still in YAML format:
```shell
svinst verilog/simple.sv --full-tree files: - filename: "verilog/simple.sv" syntaxtree: - SourceText: - Description: - ModuleDeclaration: - ModuleDeclarationAnsi: - ModuleAnsiHeader: - ModuleKeyword: - Keyword: - Token: "module" Line: 1 - ModuleIdentifier: - Identifier: - SimpleIdentifier: - Token: "A" Line: 1 - Symbol: - Token: ";" Line: 1 - Keyword: - Token: "endmodule" Line: 2 ```