Hardware Abstraction Layer for Flexible Memory Controller (FMC) on STM32H7
Currently only SDRAM functions are implemented.
This crate depends on the GPIO, Clock and Delay functionality from stm32h7xx-hal
The H7 supports up to 2 external SDRAM devices. This library currently only supports 1, although it may be on either bank 1 or 2.
IO is constructed by configuring each pin as high speed and assigning to the FMC block (usually AF12).
rust
let pa0 = gpioa.pa0.into_push_pull_output()
.set_speed(Speed::VeryHigh)
.into_alternate_af12()
.internal_pull_up(true);
Then contruct a PinSdram type from the required pins. They must be specified in the order given here.
rust
let fmc_io = stm32h7_fmc::PinsSdramBank1(
(
// A0-A11
pa0, ...
// BA0-BA1
// D0-D31
// NBL0 - NBL3
// SDCKE
// SDCLK
// SDNCAS
// SDNE
// SDRAS
// SDNWE
)
);
See the examples for an ergonomic method using macros.
First create a new SDRAM from the FMC peripheral, IO and SDRAM device constants.
rust
let mut sdram =
stm32h7_fmc::Sdram::new(dp.FMC, fmc_io, is42s32800g_6::Is42s32800g {});
Then initialise the controller and the SDRAM device. Convert the
raw pointer to a sized slice using from_raw_parts_mut.
```rust let ram = unsafe { // Initialise controller and SDRAM let ram_ptr: *mut u32 = sdram.init(&mut delay, ccdr.clocks);
// 32 MByte = 256Mbit SDRAM = 8M u32 words
slice::from_raw_parts_mut(ram_ptr, 8 * 1024 * 1024)
};
```
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