Hardware Abstraction Layer for STM32 Memory Controllers (FMC/FSMC)
Currently only SDRAM functions are implemented.
This crate is a work in progress! Contributions very welcome
(If your HAL already implements FMC, you can skip this)
See the docs
The FMC peripheral supports up to 2 external SDRAM devices. This crate currently only supports 1, although it may be on either bank 1 or 2.
External memories are defined by
SdramChip
implementations. There are several examples in the devices
folder, or you can make your own.
To pass pins to a constructor, create a tuple with the following ordering:
rust
let pins = (
// A0-A12
pa0, ...
// BA0-BA1
// D0-D31
// NBL0 - NBL3
// SDCKE
// SDCLK
// SDNCAS
// SDNE
// SDRAS
// SDNWE
);
You can leave out address/data pins not used by your memory.
If you are using a HAL, see the HAL documentation.
Otherwise you can implement
FmcPeripheral
yourself then use
Sdram::new
/
Sdram::new_unchecked
directly.
Once you have an Sdram
type, you can:
init
. This
returns a raw pointerfrom_raw_parts_mut
```rust let ram = unsafe { // Initialise controller and SDRAM let ram_ptr: *mut u32 = sdram.init(&mut delay);
// 32 MByte = 256Mbit SDRAM = 8M u32 words
slice::from_raw_parts_mut(ram_ptr, 8 * 1024 * 1024)
}; ```
TODO
TODO
If you end up depending on a fork or a newer version of this crate than the
HAL crate for your device, you can override the version pulled in by the
external crate using a [patch]
section in your Cargo.toml
, as described
in the
Cargo Book.
git commit -am 'v0.2.0'
git push origin
git tag -a 'v0.2.0' -m 'v0.2.0'
git push origin v0.2.0
cargo publish
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