Hardware Abstraction Layer for STM32 Memory Controllers (FMC/FSMC)
Currently only SDRAM functions are implemented.
This crate is a work in progress! Contributions very welcome
The hardware supports up to 2 external SDRAM devices. This library currently only supports 1, although it may be on either bank 1 or 2.
To pass pins to
Sdram::new,
create a tuple with the following ordering:
rust
let pins = (
// A0-A11
pa0, ...
// BA0-BA1
// D0-D31
// NBL0 - NBL3
// SDCKE
// SDCLK
// SDNCAS
// SDNE
// SDRAS
// SDNWE
);
External memories are defined by SdramChip implementations. There are already
several examples in the devices/ folder.
TODO
TODO
See the docs
Follow the documention in your HAL to initialise the FMC.
Once you have an Sdram type from your HAL, you can:
from_raw_parts_mut```rust let ram = unsafe { // Initialise controller and SDRAM let ram_ptr: *mut u32 = sdram.init(&mut delay, ccdr.clocks);
// 32 MByte = 256Mbit SDRAM = 8M u32 words
slice::from_raw_parts_mut(ram_ptr, 8 * 1024 * 1024)
}; ```
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