Rust Litex HAL

A Rust embedded HAL crate for LiteX cores. It contains basic HAL traits for GPIO, UART, SPI, and delay.

ULX3S demo

More info and instructions on my blog and example project in this repo

The repository also contains an example that you can run on Verilator using litex_sim.

Compiling and simulating the example

Compilation

The following dependencies are required to generate Rust code for peripherals (also called Peripheral Access Crate or PAC) and build the example for it.

Rust target for RISCV 32I

Our example use VexRiscv, so to be able to compile them you need to add riscv32i-unknown-none-elf target for Rust.

bash rustup target add riscv32i-unknown-none-elf

Python

For LiteX scripts.

bash sudo pacman -S python

bash sudo apt install python3

Official instructions.

LiteX

To build cores and optionally simulate it using verilator.

Official instructions.

Simulation on litex_sim

The following dependencies are required if you want to run the example on litex_sim.

Cross compiler for RISCV 32I

To compile VexRiscv soft core. RISCV 64 can also build RISCV 32.

bash sudo pacman -S riscv64-elf-gcc

bash sudo apt install gcc-riscv64-unknown-elf

Verilator

Simulator to run simulation.

bash sudo pacman -S verilator

bash sudo apt install verilator

LLVM tools

LLVM tools, needed to convert the example from ELF to BIN.

bash rustup component add llvm-tools-preview

cargo-make

Rust task runner and build tool, needed to automate simulation.

bash cargo install --no-default-features cargo-make

bash paru -S cargo-make

cargo-binutils

Cargo subcommands to invoke the LLVM tools, needed to convert the example from ELF to BIN.

bash cargo install cargo-binutils

bash paru -S cargo-binutils

Simulation

To run the simulation execute the following command:

bash cargo make simulate --example counter

You can pass additional Cargo flags such as --release at the end of the simulation command.