Low-level register mappings for the Silicon Labs EFM32PG1B family of ARM Cortex-M4 microcontrollers, written in Rust. The code is generated automatically from a vendor-supplied SVD file, using svd2rust.
The purpose of this crate is to give embedded programs or libraries written Rust access to the complete functionality of EFM32PG1B MCUs.
This PAC is closely based on Timo Kröger's PAC for the efm32pg12 microcontrollers.
The SVD file used is based on all the files in the EFM32PG1B CMSIS-Pack. The only differences between them are the <name>, <description> and <flashSize> field values. Here are the flash sizes for each MCU:
| EFM32PG1B | flashSize |
| ----------- | :-------: |
| 100F128GM32 | 0x20000 |
| 100F128IM32 | 0x20000 |
| 100F256GM32 | 0x40000 |
| 100F256IM32 | 0x40000 |
| 200F128GM32 | 0x20000 |
| 200F128GM48 | 0x20000 |
| 200F128IM32 | 0x20000 |
| 200F256GM32 | 0x40000 |
| 200F256GM48 | 0x40000 |
| 200F256IM32 | 0x40000 |
| 200F256IM48 | 0x40000 |
The flashSize value used in the source EFM32PG1B.svd file was set to the lowest value (0x20000).
The ASYNC (Asynchronous Reflex) field for all Channel Control Registers of the Clock Management Unit has been renamed to ASYNCREFL because svd2rust converted it to async, which is a rust keyword, and caused compilation errors.
SVD files are available in the EFM32PG1B CMSIS-Pack.
Additional vendor supplied documents: - Datasheet - Reference Manual - Errata
Licensed under either of
Apache License, Version 2.0 (LICENSE-APACHE or http://www.apache.org/licenses/LICENSE-2.0)
MIT license (LICENSE-MIT or http://opensource.org/licenses/MIT)
at your option.
Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.