Atomic operations on potentially uninitialized integers.
Copying types containing uninitialized bytes (e.g., padding), via the standard library's atomic types is undefined behavior because the copy goes through integers.
This crate provides a way to soundly perform such operations.
Currently, x86, x86_64, ARMv7, ARMv8, AArch64, and RISC-V are supported.
| targetarch | primitives | [load]/[store] | [swap] | | --------------- | --------------------------------------------------- |:--------------:|:------:| | x86 | isize,usize,i8,u8,i16,u16,i32,u32 | ✓ | ✓ | | x8664 | isize,usize,i8,u8,i16,u16,i32,u32,i64,u64 | ✓ | ✓ | | arm (v7,v8) | isize,usize,i8,u8,i16,u16,i32,u32 | ✓ | ✓ | | arm (v7-a) | i64,u64 | ✓ | ✓ | | aarch64 | isize,usize,i8,u8,i16,u16,i32,u32,i64,u64,i128,u128 | ✓ | ✓[1] | | riscv32 | isize,usize,i32,u32 | ✓ | ✓[2] | | riscv32 | i8,u8,i16,u16 | ✓ | | | riscv64 | isize,usize,i32,u32,i64,u64 | ✓ | ✓[2] | | riscv64 | i8,u8,i16,u16 | ✓ | |
[1] If the lse target feature is enabled at compile-time, more efficient instructions are used instead of increasing the CPU requirement to ARMv8.1+.
[2] RISC-V's atomic swap is not available on targets without the A (or G) extension such as riscv32i-unknown-none-elf, riscv32imc-unknown-none-elf, etc.
Feel free to submit an issue if your target is not supported yet.
Licensed under either of Apache License, Version 2.0 or MIT license at your option.
Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.